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K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 1 document title 8m x 8 bit nand flash memory revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to cha nge the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you have any questio ns, please contact the samsung branch office near you. revision no. 0.0 1.0 1.1 1.2 1.3 remark preliminary final final final final history initial issue. data sheet, 1998 data sheet. 1999 1) added ce don?t care mode during the data-loading and reading 1) revised real-time map-out algorithm(refer to technical notes) changed device name - km29u64000t -> K9F6408U0M-TCB0 - km29u64000it -> k9f6408u0m-tib0 draft date april 10th 1998 july 14th 1998 april 10th 1999 july 23th 1999 sep. 15th 1999
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 2 8m x 8 bit nand flash memory the k9f6408u0m is a 8m(8,388,608)x8bit nand flash mem- ory with a spare 256k(262,144)x8bit. its nand cell provides the most cost-effective solution for the solid state mass storage market. a program operation programs the 528-byte page in typically 200 m s and an erase operation can be performed in typ- ically 2ms on an 8k-byte block. data in the page can be read out at 50ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command inputs. the on-chip write controller automates all program and erase functions including pulse repetition, where required, and inter- nal verify and margining of data. even the write-intensive sys- tems can take advantage of the k9f6408u0m s extended reliability of 1,000,000 program/erase cycles by providing either ecc(error correcting code) or real time mapping-out algo- rithm. these algorithms have been implemented in many mass storage applications and also the spare 16 bytes of a page combined with the other 512 bytes can be utilized by system- level ecc. the k9f6408u0m is an optimum solution for large nonvolatile storage applications such as solid state file storage, digital voice recorder, digital still camera and other portable applica- tions requiring non-volatility. general description features voltage supply : 2.7v ~ 3.6v organization - memory cell array : (8m + 256k)bit x 8bit - data register : (512 + 16)bit x8bit automatic program and erase - page program : (512 + 16)byte - block erase : (8k + 256)byte 528-byte page read operation - random access : 7 m s(max.) - serial page access : 50ns(min.) fast write cycle time - program time : 200 m s(typ.) - block erase time : 2ms(typ.) command/address/data multiplexed i/o port hardware data protection - program/erase lockout during power transitions reliable cmos floating-gate technology - endurance : 1m program/erase cycles - data retention : 10 years command register operation 44(40) - lead tsop type ii (400mil / 0.8 mm pitch) pin configuration v ss cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o0 i/o1 i/o2 i/o3 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 v cc q i/o4 i/o5 i/o6 i/o7 n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c se r/ b re ce v cc 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44(40) tsop (ii) standard type note : connect all v cc , v cc q and v ss pins of each device to power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o0 ~ i/o7 data input/outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect se spare area enable r/ b ready/busy output v cc power(2.7v ~ 3.6v) v cc q output buffer power(2.7v~3.6v or 5.0v) v ss ground n.c no connection pin description
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 3 512b column 16 byte column figure 1. functional block diagram figure 2. array organization note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the starting address of the 2nd half of the register. * a 8 is internally set to "low" or "high" by the 00h or 01h command. * x can be high or low. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 *x *x v cc x-buffers y-gating 64m + 2m bit command 2nd half page register & s/a nand flash array (512 + 16)byte x 16384 y-gating 1st half page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 9 - a 22 a 0 - a 7 command ce re we cle ale wp i/0 0 i/0 7 v cc q v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 16k row (=1024 block) 512 byte 8 bit 16 byte 1 block(=16 row) (8k + 256) byte i/o 0 ~ i/o 7 1 page = 528 bytes 1 block = 528 bytes x 16 pages = (8k + 256) bytes 1 device = 528 bytes x 16pages x 1024 blocks = 66 mbits column address row address (page address) page register
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 4 product introduction the k9f6408u0m is a 66mbit(69,206,016 bit) memory organized as 16,384 rows by 528 columns. spare sixteen columns are located from column address of 512 to 527. a 528-byte data register is connected to memory cell arrays accommodating data trans- fer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected to form a nand structure. each of the 16 cells resides in a different page. a block consists of the 16 pages formed by one nand structures, totaling 4,224 nand structures of 16 cells. the array organization is shown in figure 2. th e program and read operations are executed on a page basis, while the erase operation is executed on a block basis. the memory array consists of 1024 separately erasable 8k-byte blocks. it indicates that the bit by bit erase operation is prohibited on the k9f6408u0m. the k9f6408u0m has addresses multiplexed into 8 i/o s. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. command, address and data are all written throug h i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. all commands require one bus cycle except for block erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block address loading. the 8m byte physical space requires 23 addresses, thereby requiring three cycles for byte-level addressing: col - umn address, low row address and high row address, in that order. page read and page program need the same three address cycles following the required command input. in block erase operation, however, only the two row address cycles are used. device operations are selected by writing specific commands into the command register. table 1 defines the specific commands of the k9f6408u0m. table 1. command sets note : 1. the 00h command defines starting address of the 1st half of registers. the 01h command defines starting address of the 2nd half of registers. after data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. 2. the 50h command is valid only when the se (pin 40) is low level. function 1st. cycle 2nd. cycle acceptable command during busy sequential data input 80h - read 1 00h/01h (1) - read 2 50h (2) - read id 90h - reset ffh - o page program 10h - block erase 60h d0h read status 70h - o
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 5 pin description command latch enable(cle) the cle input controls the path activation for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. address latch enable(ale) the ale input controls the path activation for address and input data to the internal address/data register. addresses are latched on the rising edge of we with ale high, and input data is latched when ale is low. chip enable( ce ) the ce input is the device selection control. when ce goes high during a read operation the device is returned to standby mode. however, when the device is in the busy state during program or erase, ce high is ignored, and does not return the device to standby mode. write enable( we ) the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. read enable( re ) the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the falling ed ge of re which also increments the internal column address counter by one. spare area enable( se ) the se input controls the spare area selection when se is high, the device is deselected the spare area during read1, sequential data input and page program. i/o port : i/o 0 ~ i/o 7 the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to high- z when the chip is deselected or when the outputs are disabled. write protect( wp ) the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. ready/ busy (r/ b ) the r/ b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. power line(v cc & v cc q) the v cc q is the power supply for i/o interface logic. it is electrically isolated from main power line(v cc =2.7v~3.6v) for supporting 5v tolerant i/o with 5v power supply at v cc q.
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 6 dc and operating characteristics (recommended operating conditions otherwise noted.) parameter symbol test conditions min typ max unit operating current sequential read i cc 1 tcycle=50ns, ce =v il , i out =0ma - 10 20 ma program i cc 2 - - 10 20 erase i cc 3 - - 10 20 stand-by current(ttl) i sb 1 ce =v ih , wp = se =0v/v cc - - 1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp = se =0v/v cc - 10 50 m a input leakage current i li v in =0 to 3.6v - - 10 output leakage current i lo v out =0 to 3.6v - - 10 input high voltage v ih i/o pins 2.0 - v cc q+0.3 v except i/o pins 2.0 - v cc +0.3 input low voltage, all inputs v il - -0.3 - 0.8 output high voltage level v oh i oh =-400 m a 2.4 - - output low voltage level v ol i ol =2.1ma - - 0.4 output low current(r/ b ) i ol (r/ b ) v ol =0.4v 8 10 - ma absolute maximum ratings note : 1. minimum dc voltage is -0.3v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc q+0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in -0.6 to + 6.0 v v cc -0.6 to + 4.6 v v cc q -0.6 to + 6.0 v temperature under bias K9F6408U0M-TCB0 t bias -10 to + 125 c k9f6408u0m-tib0 -40 to + 125 storage temperature t stg -65 to + 150 c short circuit output current i os 5 ma recommended operating conditions (voltage reference to gnd, K9F6408U0M-TCB0:t a =0 to 70 c, k9f6408u0m-tib0:t a =-40 to 85 c) note : 1. v cc and v cc q pins are separated each other. parameter symbol min typ. max unit supply voltage v cc 2.7 3.3 3.6 v supply voltage v cc q *1 2.7 - 5.5 v supply voltage v ss 0 0 0 v
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 7 mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. 3. when se is high, spare area is deselected. cle ale ce we re se wp mode h l l h x x read mode command input l h l h x x address input(3clock) h l l h x h write mode command input l h l h x h address input(3clock) l l l h l/h (3) h data input l l l h l/h (3) x sequential read & data output l l l h h l/h (3) x during read(busy) x x x x x l/h (3) h during program(busy) x x x x x x h during erase(busy) x x (1) x x x x l write protect x x h x x 0v/v cc (2) 0v/v cc (2) stand-by capacitance ( t a =25 c, v cc =3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the k9f6408u0m may include invalid blocks. invalid blocks are defined as blocks that contain one or more bad bits. do not try to access these invalid blocks for program and erase. during its lifetime of 10 years and/or 1million program/erase cycles,the minimum number of valid blocks are guaranteed though its initial number could be reduced. (refer to the attached technical notes) 2. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block parameter symbol min typ. max unit valid block number n vb 1014 1020 1024 blocks program/erase characteristics parameter symbol min typ max unit program time t prog - 200 1000 m s number of partial program cycles in the same page nop - - 10 cycles block erase time t bers - 2 4 ms ac test condition (K9F6408U0M-TCB0:t a =0 to 70 c, k9f6408u0m-tib0:t a =-40 to 85 c, v cc =2.7v~3.6v unless otherwise noted) parameter value input pulse levels 0.4v to 2.4v input rise and fall times 5ns input and output timing levels 0.8v and 2.0v output load (3.0v +/-10%) 1 ttl gate and cl = 50pf output load (3.3v +/-10%) 1 ttl gate and cl = 100pf
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 8 ac characteristics for operation note : 1. if ce goes high within 30ns after the rising edge of the last re , r/ b will not return to v ol . 2. the time to ready depends on the value of the pull-up resistor tied r/ b pin. 3. to break the sequential read cycle, ce must be held high for longer time than tceh. parameter symbol min max unit data transfer from cell to register t r - 7 m s ale to re delay( id read ) t ar1 100 - ns ale to re delay(read cycle) t ar2 50 - ns ce to re delay( id read) t cr 100 - ns ready to re low t rr 20 - ns re pulse width t rp 30 - ns we high to busy t wb - 100 ns read cycle time t rc 50 - ns re access time t rea - 35 ns re high to output hi-z t rhz 15 30 ns ce high to output hi-z t chz - 20 ns re high hold time t reh 15 - ns output hi-z to re low t ir 0 - ns last re high to busy(at sequential read) t rb - 100 ns ce high to ready(in case of interception by ce at read) (1) t cry - 50 +tr(r/ b ) (2) ns ce high hold time(at the last serial read) (3) t ceh 100 - ns re low to status output t rsto - 35 ns ce low to status output t csto - 45 ns we high to re low t whr 60 - ns re access time(read id) t readid - 35 ns device resetting time (read/program/erase) t rst - 5/10/500 m s ac timing characteristics for command / address / data input parameter symbol min max unit cle set-up time t cls 0 - ns cle hold time t clh 10 - ns ce setup time t cs 0 - ns ce hold time t ch 10 - ns we pulse width t wp 25 - ns ale setup time t als 0 - ns ale hold time t alh 10 - ns data setup time t ds 20 - ns data hold time t dh 10 - ns write cycle time t wc 50 - ns we high hold time t wh 15 - ns
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 9 identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. typic ally, an invalid block will contain a single bad bit. the information regarding the invalid block(s) is called as the invalid block in formation. the invalid block information is written to the 1st or the 2nd page of the invalid block(s) with 00h data. devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s ) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a selec t tran- sistor. the system design must be able to mask out the invalid block(s) via address mapping. the 1st block of the nand flash, ho w- ever, is fully guaranteed to be a valid block. nand flash technical notes all device locations are erased(ffh) except locations where the invalid block information is written prior to shipping. since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table via the following suggested flow chart(figure 1). any intentional era- sure of the original invalid block information is prohibited. * check "ffh" on the 1st and 2nd page figure 1. flow chart to create invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no invalid block(s) table
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 10 nand flash technical notes (continued) program flow chart start sr. 6 = 1 ? write 00h sr. 0 = 0 ? no * if ecc is used, this verification write 80h write address write data write 10h write 70h write address wait for tr time verify data no program completed or r/b = 1 ? program error yes no yes * program error yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * operation is not needed. error in write or read operation over its life time, the additional invalid blocks may occur. through the tight process control and intensive testing, samsung mi ni- mizes the additional block failure rate, which is projected below 0.1% up until 1million program/erase cycles. refer to the qual ification report for the actual data.the following possible failure modes should be considered to implement a highly reliable system. in t he case of status read failure after erase or program, block replacement should be done. to improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ecc without any block replacement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after program) --> block replacement or ecc correction read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 11 erase flow chart start sr. 6 = 1 ? sr. 0 = 0 ? no * write 60h write block address write d0h write 70h or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes block replacement when the error happens in block "a", try to write the data into another block "b" by reloading from an exter- nal buffer. then, prevent further system access to block "a"(by creating a "invalid block" table or other appropriate scheme.) buffer memory error occurs block a block b nand flash technical notes (continued)
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 12 pointer operation of k9f6408u0m the k9f6408u0m has three read modes to set the destination of the pointer. the pointer is set to "a" area by the "00h" command, to "b" area by the "01" command, and to "c" area by the "50h" command. table 1 shows the destination of the pointer, and figure 2 shows the block diagram of its operations. example of pointer operation programming "a" area 50h "c" area (1) "a" area program "a" area address / data input 256 byte table 1. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) (00h plane) "b" area (01h plane) "c" area (50h plane) 256 byte 16 byte "a" "b" "c" internal page buffer pointer select commnad (00h, 01h, 50h) pointer figure 2. block diagram of pointer operation table 2. pointer status after each operation * 01h command is valid just one time when it is used as a pointer for program/erase. operation pointer status after operation program/erase reset power up with previous 00h, device is set to 00h plane with previous 01h, device is set to 00h plane* with previous 50h, device is set to 50h plane "00h" plane("a" area) "00h" plane("a" area) 00h 80h "a" area program 00h "a" area (2) "b" area program "b" area address / data input 01h 80h "a" area program 00h "a" area (3) "c" area program "c" area address / data input 50h 80h "c" area program 10h 80h 10h 10h 80h 10h 10h 80h 10h address / data input address / data input address / data input "a" area program "b" area program "c" area program
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 13 system interface using ce don?t-care. ce we t wp t ch timing requirements : if ce is is exerted high during data-loading, tcs must be minimum 10ns and twc must be increased accordingly. t cs (min. 10ns) start add.(3cycle) 80h data input ce cle ale we i/o 0 ~ 7 data input ce don?t-care ? ? 10h for a easier system interface, ce may be inactive during the data-loading or sequential data-reading as shown below. the interna l 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. in addition , for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce during the data-loading and re ad- ing would provide significant savings in power consumption. start add.(3cycle) 00h ce cle ale we i/o 0 ~ 7 data output(sequential) ce don?t-care ? r/ b t r re t cea out t rea (max. 45ns) ce re i/o 0 ~ 7 timing requirements : if ce is is exerted high during sequential data-reading, the falling edge of ce to valid data(tcea) must be kept greater than 45ns. figure 3. program operation with ce don?t-care. figure 4. read operation with ce don?t-care.
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 14 * command latch cycle ce we cle ale i/o 0 ~ 7 command * address latch cycle ce we cle ale i/o 0 ~ 7 a 0 ~a 7 a 9 ~a 16 a 17 ~a 22 t cls t cs t clh t ch t wp t als t alh t ds t dh t cls t cs t wc t wc t wp t wp t wh t wh t als t alh t ds t dh t ds t dh t ds t dh t wp
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 15 * input data latch cycle ce cle we i/o 0 ~ 7 din 0 din 1 din 511 ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp * s equential out cycle after read (cle=l, we =h, ale=l) re ce r/ b i/o 0 ~ 7 dout dout dout t rc t rea t rr t rhz* t rea t reh t rea t chz* t rhz t rp ? notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested.
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 16 * status read cycle ce we cle re i/o 0 ~ 7 70h status output t cls t clh t cs t wp t ch t ds t dh t rsto t ir t rhz t chz t whr t csto t cls read1 operation (read one page) ce cle r/ b i/o 0 ~ 7 we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 22 dout n dout n+1 dout n+2 dout n+3 dout 527 column address page(row) address t wb t ar2 t r t rc t rhz t rr t chz t ceh t rb t cry t wc ? ? ?
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 17 read1 operation (intercepted by ce ) ce cle r/ b i/o 0 ~ 7 we ale re busy trr 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 22 dout n dout n+1 dout n+2 dout n+3 page(row) address address column t wb t ar2 t chz t r t rr t rc read2 operation (read one page) ce cle r/ b i/o 0 ~ 7 we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 22 dout dout 527 m address a 0 ~ a 3 :valid address a 4 ~ a 7 :dont care 511+m dout 511+m+1 selected row start address m 512 16 t ar2 t r t wb t rr ? ? ?
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 18 sequential row read operation ce cle r/ b i/o 0 ~ 7 we ale re 00h a 0 ~ a 7 busy m output a 9 ~ a 16 a 17 ~ a 22 dout n dout n+1 dout n+2 dout 527 dout 0 dout 1 dout 2 dout 527 busy m+1 output n page program operation ce cle r/ b i/o 0 ~ 7 we ale re 80h 70h i/o 0 din n din din 10h 527 n+1 a 0 ~ a 7 a 17 ~ a 22 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data sequential input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc ? ? ? ? ? ? ? ? ?
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 19 block erase operation (erase one block) ce cle r/ b i/o 0 ~ 7 we ale re 60h a 17 ~ a 22 a 9 ~ a 16 auto block erase setup command erase command read status command i/o 0 =0 successful erase i/o 0 =1 error in erase doh 70h i/o 0 busy manufacture & device id read operation ce cle i/o 0 ~ 7 we ale re 90h read id command maker code device code 00h ech e6h t wb t bers t wc t wc t readid block address ?
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 20 device operation page read upon initial device power up, the device defaults to read1 mode. this operation is also initiated by writing 00h to the command reg- ister along with three address cycles. once the command is latched, it does not need to be written for the following page read o per- ation. three types of operations are available : random read, serial page read and sequential row read. the random read mode is enabled when the page address is changed. the 528 bytes of data within the selected page are trans- ferred to the data registers in less than 7 m s(tr). the cpu can detect the completion of this data transfer(tr) by analyzing the output of r/ b pin. once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing re . high to low transitions of the re clock output the data stating from the selected column address up to the last column address(col- umn 511 or 527 depending on the state of se pin). after the data of last column address is clocked out, the next page is automatically selected for sequential row read. waiting 7 m s again allows reading the selected page.the sequential row read operation is terminated by bringing ce high. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of bytes 512 t o 527 may be selectively accessed by writing the read2 command with se pin low. addresses a 0 to a 3 set the starting address of the spare area while addresses a 4 to a 7 are ignored. unless the operation is aborted, the page address is automatically incremented for sequential row read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the read1 com- mand(00h/01h) is needed to move the pointer back to the main area. figures 3 thru 6 show typical sequence and timings for each read operation. figure 3. read1 operation start add.(3cycle) 00h 01h a 0 ~ a 7 & a 9 ~ a 22 data output(sequential) (00h command) 1st half array 2nd half array data field spare field (01h command)* 1st half array 2nd half array data field spare field * after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. ce cle ale r/ b we i/o 0 ~ 7 re t r
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 21 figure 5. sequential row read1 operation figure 4. read2 operation 50h a 0 ~ a 3 & a 9 ~ a 22 data output(sequential) spare field ce cle ale r/ b we 1st half array 2nd half array data field spare field ( se =l, 00h command) 1st half array 2nd half array data field spare field 00h 01h a 0 ~ a 7 & a 9 ~ a 22 i/o 0 ~ 7 r/ b start add.(3cycle) start add.(3cycle) data output data output data output 1st 2nd nth (528 byte) (528 byte) (a 4 ~ a 7 : don't care) 1st 2nd nth ( se =l, 01h command) 1st half array 2nd half array data field spare field 1st 2nd nth ( se =h, 00h command) 1st half array 2nd half array data field spare field 1st 2nd nth i/o 0 ~ 7 re t r t r t r t r ?
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 22 figure 6. sequential row read2 operation ( se =fixed low) page program the device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528, in a single page program cycle. the number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed ten. the addressing may be done in any random order in a block. a page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page registe r, fol- lowed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. serial data loading ca n be started from 2nd half array by moving pointer. about the pointer operation, please refer to the attached technical notes. the serial data loading period begins by inputting the serial data input command(80h), followed by the three cycle address input and then serial data loading. the bytes other than those to be programmed do not need to be loaded.the page program confirm com- mand(10h) initiates the programming process. writing 10h alone without previously entering the serial data will not initiate the pro- gramming process. the internal write controller automatically executes the algorithms and timings necessary for program and veri fy, thereby freeing the cpu for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the cpu can detect the completion of a program cycle by monitoring the r/ b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit(i/o 0) may be checked(figure 7). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read status command mode until another valid command is written to the command register. 50h a 0 ~ a 3 & a 9 ~ a 22 i/o 0 ~ 7 r/ b start add.(3cycle) data output data output data output 2nd nth (16 byte) (16 byte) 1st half array 2nd half array data field spare field 1st 2nd nth (a 4 ~ a 7 : don t care) 1st figure 7. program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 22 i/o 0 ~ 7 r/ b address & data input i/o 0 pass 528 byte data 10h 70h fail t r t r t r t prog ?
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 23 figure 8. block erase operation block erase the erase operation is done on a block(8k byte) basis. block address loading is accomplished in two cycles initiated by an erase setup command(60h). only address a 13 to a 22 is valid while a 9 to a 12 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase, erase-verify and pu lse repetition where required. when the erase operation is completed, the write status bit(i/o 0) may be checked. figure 8 details the sequence. 60h block add. : a 9 ~ a 22 i/o 0 ~ 7 r/ b address input(2cycle) i/o 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle output s the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, a read command(00h or 50h) should be given before sequential page read cycle. sr status definition i/o 0 program / erase "0" : successful program / erase "1" : error in program / erase i/o 1 reserved for future use "0" i/o 2 "0" i/o 3 "0" i/o 4 "0" i/o 5 "0" i/o 6 device operation "0" : busy "1" : ready i/o 7 write protect "0" : protected "1" : not protected table2. status register definition
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 24 figure 9. read id operation read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code (e6h) respectively. the command regis- ter remains in read id mode until further commands are issued to it. figure 9 shows the operation sequence. ce cle i/o 0 ~ 7 ale re we 90h 00 ech e6h address. 1 cycle maker code device code t cr t ar1 t readid figure 10. reset operation reset the device contains a status register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle output s the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce dose not need to be toggled for updated status. refer to table 2 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, a read command(00h or 50h) should be given before sequential page read cycle. after power-up after reset operation mode read 1 waiting for next command ffh i/o 0 ~ 7 r/ b table3. device status t rst
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 25 data protection the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 2v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down as shown in figure 11. the two step command sequence for program/erase provides additional software protection. figure 11. ac waveforms for power transition ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. it returns to high when the internal controller has finished the operatio n. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. an appropriate pull-up resister is required for proper operation and the value may be calculated by the following equation. rp = v cc r/ b open drain output device gnd v cc (max.) - v ol (max.) i ol + ? i l = 3.2v 8ma + ? i l where i l is the sum of the input currents of all devices tied to the r/ b pin. v cc wp high ? ? ~ 2.5v ~ 2.5v
K9F6408U0M-TCB0, k9f6408u0m-tib0 flash memory 26 package dimensions unit :mm/inch 0~8 0 . 0 0 2 0.805 #1 44(40) lead plastic thin small out-line package type(ii) 0 . 0 5 #22(20) #44(40) #23(21) 0.032 0.35 0.10 0.014 0.004 0.80 0.0315 m i n . 0 . 0 4 7 1 . 2 0 m a x . 0.741 18.81 max. 18.41 0.10 0.725 0.004 +0.10 -0.05 +0.004 -0.002 0.15 0.006 1 0 . 1 6 0 . 4 0 0 44(40) - tsop2 - 400f 0.10 0.004 0.50 0.020 0.25 0.010 typ 0 . 4 5 ~ 0 . 7 5 0 . 0 1 8 ~ 0 . 0 3 0 0 . 0 3 9 0 . 0 0 4 1 . 0 0 0 . 1 0 max 1 1 . 7 6 0 . 2 0 0 . 4 6 3 0 . 0 0 8 ( )

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